The hole (via) is one of the important components of the multi-layer PCB circuit board, and the cost of drilling usually accounts for 30% to 40% of the cost of the PCB board. Simply put, every hole on a PCB can be called a via.

In terms of function, vias can be divided into two categories:

• One is for electrical connection between layers.
• The second is to use as a fixation or positioning of the device.

In terms of process, these vias are generally divided into three categories, namely blind via, buried via and through via.

Blind hole
Located on the top and bottom surfaces of a printed circuit board, it has a certain depth and is used for the connection of the surface layer and the underlying inner layer. The depth of the hole usually does not exceed a certain ratio (diameter).

Buried via
Refers to the connection hole located on the inner layer of the printed circuit board, which does not extend to the surface of the circuit board. The above two types of holes are located in the inner layer of the circuit board, and are completed by the through hole forming process before lamination. During the formation of the via hole, several inner layers may be overlapped.

Through hole
This hole runs through the entire board and can be used for internal interconnection or as a mounting hole for components.
Because the through hole is easier to realize in the process and the cost is lower, most of the printed circuit boards use it instead of the other two kinds of through holes. The via holes mentioned below are considered as through holes unless otherwise specified.

From a design point of view, a via is mainly composed of two parts, one is the drill hole in the middle, and the other is the pad area around the drill hole. The size of these two parts determines the size of the via.

Obviously, in high-speed, high-density PCB design, it is always hoped that the smaller the via hole, the better, so that more wiring space can be left on the board. In addition, the smaller the via hole, the smaller its own parasitic capacitance. , more suitable for high-speed circuits.

However, the reduction in hole size also brings an increase in cost, and the size of the via hole cannot be reduced indefinitely. It is limited by process technologies such as drilling and plating: the smaller the hole, the more drilling The longer the hole takes, the easier it is to deviate from the center; and when the depth of the hole exceeds 6 times the diameter of the drilled hole, it is not guaranteed that the hole wall will be uniformly plated with copper.

For example, if the thickness of a normal 6-layer PCB board (through hole depth) is 50Mil, then under normal conditions, the hole diameter that the PCB manufacturer can provide can only reach 8Mil.

With the development of laser drilling technology, the size of the drill hole can also become smaller and smaller. Generally, the via hole with a diameter of less than or equal to 6Mil is called a micro hole. Microvias are often used in HDI (High Density Interconnection) designs. Microvia technology allows vias to be directly punched on the pad (Via-in-pad), which greatly improves circuit performance and saves wiring space.

Vias appear as discontinuous discontinuities in impedance on the transmission line, causing signal reflection. Generally, the equivalent impedance of the via is about 12% lower than that of the transmission line. For example, the impedance of a 50-ohm transmission line will decrease by 6 ohms when passing through the via (specifically, it is related to the size of the via and the thickness of the board, not reduction).

However, the reflection caused by the discontinuous impedance of the via is actually very small, and the reflection coefficient is only:
(44-50)/(44+50)=0.06
Problems arising from vias are more focused on the effects of parasitic capacitance and inductance.

Parasitic capacitance of vias
The via itself has parasitic capacitance to the ground. If it is known that the diameter of the isolation hole of the via on the ground layer is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε, the parasitic capacitance of the via is approximated by:
C=1.41εTD1/(D2-D1)

The main effect of the parasitic capacitance of the via on the circuit is to prolong the rise time of the signal and reduce the speed of the circuit.

For example, for a PCB board with a thickness of 50Mil, if a via hole with an inner diameter of 10Mil and a pad diameter of 20Mil is used, and the distance between the pad and the ground copper area is 32Mil, we can use the above formula to approximately calculate the via hole The parasitic capacitance is roughly:
C=1.41×4.4×0.050×0.020/(0.032-0.020)=0.517pF

The rise time change caused by this part of the capacitance is:
T10-90=2.2C(Z0/2)=2.2×0.517x(55/2)=31.28ps

From these values, it can be seen that although the effect of the rise delay caused by the parasitic capacitance of a single via is not very obvious, if the via is used multiple times in the trace to switch between layers, the EDA365 electronic forum reminds the designer to still carefully considered.

Parasitic inductance of vias

Similarly, parasitic capacitance exists in vias and parasitic inductance also exists. In the design of high-speed digital circuits, the harm caused by parasitic inductance of vias is often greater than the influence of parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and reduce the filtering effect of the entire power system.

We can easily calculate the approximate parasitic inductance of a via with the following formula:
L=5.08h[ln(4h/d)+1]

where L is the inductance of the via, h is the length of the via, and d is the diameter of the center drilled hole. It can be seen from the formula that the diameter of the via hole has little effect on the inductance, while the length of the via hole affects the inductance.

Still using the above example, the inductance of the via can be calculated as:
L=5.08×0.050[ln(4×0.050/0.010)+1]=1.015nH

If the rise time of the signal is 1ns, then its equivalent impedance is:
XL=πL/T10-90=3.19Ω

Such impedance can no longer be ignored when high-frequency current passes through. It should be noted that the bypass capacitor needs to pass through two vias when connecting the power supply layer and the ground layer, so that the parasitic inductance of the vias will be multiplied.

Via Design in High Speed ​​PCB

Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to circuit design. In order to reduce the parasitic vias In order to avoid the adverse effects caused by the effect, the following aspects can be achieved as far as possible in the design:
Considering both cost and signal quality, select vias of reasonable size. For example, for 6-10-layer memory module PCB design, it is better to use 10/20Mil (drilling/pad) vias. For some high-density small-sized boards, you can also try to use 8/18Mil vias. hole.

Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, consider using larger sizes to reduce impedance.

From the two formulas discussed above, it can be concluded that using a thinner PCB board is beneficial to reduce two parasitic parameters of vias.

The power and ground pins should be drilled with vias as close as possible. The shorter the leads between the vias and the pins, the better, because they will increase the inductance. At the same time, the leads of power and ground should be as thick as possible to reduce impedance.

The signal traces on the PCB should not change layers as much as possible, which means that unnecessary vias should be minimized.

Place some ground vias near the vias where the signal transitions to provide a close return path for the signal. It is even possible to place a few redundant ground vias on the PCB in large numbers. Of course, flexibility is also required in the design.

The via model discussed earlier is the case where each layer has pads. Sometimes, we can reduce or even remove the pads of some layers.

Especially in the case of a very high density of vias, it may lead to the formation of a circuit breaker on the copper layer. To solve this problem, in addition to moving the position of the via, we can also consider placing the via on the copper layer. The pad size is reduced.

How to use vias: Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, improper use of seemingly simple vias often brings great negative effects to circuit design.

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