Via is one of the important components of multi-layer PCB circuit boards, and the cost of drilling usually accounts for 30% to 40% of the cost of PCB manufacturing. Simply put, every hole on the PCB can be called a via.
30% to 40% of the cost of plate making. Simply put, every hole on the PCB can be called a via.
From the point of view of function, vias can be divided into two categories:
- One is used as electrical connection between layers
- The second is to fix or locate the device
In terms of process, these vias are generally divided into three categories, namely blind vias, buried vias and through vias.
(1) Blind holes:
located on the top and bottom surfaces of the printed circuit board, with a certain depth, used for the connection of the surface line and the underlying inner line, the depth of the hole usually does not exceed a certain ratio (aperture).
(2) Buried hole:
refers to the connection hole located in the inner layer of the printed circuit board, which does not extend to the surface of the circuit board. The above-mentioned two types of holes are located in the inner layer of the circuit board, and are completed by a through-hole forming process before lamination, and several inner layers may be overlapped during the formation of the via.
(3) Through hole
This kind of hole penetrates the entire circuit board and can be used for internal interconnection or as a component installation positioning hole.
Because the through hole is easier to implement in the process and the cost is lower, most of the printed circuit boards use it instead of the other two types of through holes. The following via holes, unless otherwise specified, are considered as via holes. From a design point of view, a via is mainly composed of two parts, one is the drill hole in the middle, and the other is the pad area around the drill hole. The size of these two parts determines the size of the via.
Obviously, in high-speed, high-density PCB design, it is always desirable to make the vias as small as possible, so that more wiring space can be left on the board. In addition, the smaller the vias, the smaller the parasitic capacitance of their own. , More suitable for high-speed circuits.
However, the reduction of hole size also brings about an increase in cost, and the size of vias cannot be reduced indefinitely. It is restricted by process technologies such as drilling and plating: the smaller the hole, the drill The longer the hole takes, the easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the drilled hole, it cannot be guaranteed that the hole wall can be uniformly plated with copper.
For example, if the thickness (through hole depth) of a normal 6-layer PCB board is 50Mil, then under normal conditions, the diameter of the hole that the PCB manufacturer can provide can only reach 8Mil.
With the development of laser drilling technology, the size of the hole can be smaller and smaller. Generally, a via with a diameter less than or equal to 6Mil is called a micro-hole. Microvias are often used in HDI (High Density Interconnect Structure) design. Microvia technology allows vias to be directly punched on the pad (Via-in-pad), which greatly improves circuit performance and saves wiring space.
Vias appear as breakpoints with discontinuous impedance on the transmission line, which will cause signal reflections. Generally, the equivalent impedance of the via is about 12% lower than that of the transmission line. For example, the impedance of a 50 ohm transmission line will decrease by 6 ohms when passing through the via (specifically, it is related to the size and thickness of the via, not reduction).
However, the reflection caused by the discontinuous impedance of the via is actually very small, and its reflection coefficient is only: (44-50)/(44+50)=0.06. The problems caused by the via are more concentrated on the parasitic capacitance and inductance. Influence.
（4）Parasitic capacitance of via
The via itself has a parasitic capacitance to the ground. If it is known that the diameter of the isolation hole on the ground layer of the via is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε, then the parasitic capacitance of the via is approximately:
C=1.41εTD1/(D2-D1) The main effect of the parasitic capacitance of the via hole on the circuit is to prolong the rise time of the signal and reduce the speed of the circuit.
For example, for a PCB with a thickness of 50Mil, if a via with an inner diameter of 10Mil and a pad diameter of 20Mil is used, and the distance between the pad and the ground copper area is 32Mil, then we can approximate the via using the above formula The parasitic capacitance is roughly: C=1.41×4.4×0.050×0.020/(0.032-0.020)=0.517pF
The change in rise time caused by this part of the capacitance is: T10-90=2.2C(Z0/2)=2.2×0.517x(55/2)=31.28ps
From these values, it can be seen that although the effect of the rise delay caused by the parasitic capacitance of a single via is not very obvious, if the via is used multiple times in the trace to switch between layers, it should be carefully considered.
(5) Parasitic inductance of vias
Similarly, there are parasitic inductances along with the parasitic capacitance of the vias. In the design of high-speed digital circuits, the harm caused by the parasitic inductance of the vias is often greater than the impact of the parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system.
We can use the following formula to simply calculate the parasitic inductance of a via: L=5.08h [ln(4h/d)+1]
Where L refers to the inductance of the via, h is the length of the via, and d is the diameter of the center hole. It can be seen from the formula that the diameter of the via has a small effect on the inductance, while the length of the via has an effect on the inductance.
Still using the above example, the inductance of the via can be calculated as: L=5.08×0.050[ln(4×0.050/0.010)+1]=1.015nH
If the rise time of the signal is 1ns, then the equivalent impedance is: XL=πL/T10-90=3.19Ω
Such impedance can no longer be ignored when high-frequency currents pass. Special attention should be paid to the fact that the bypass capacitor needs to pass through two vias when connecting the power plane and the ground plane, so that the parasitic inductance of the vias will increase exponentially.
(6) Via design in high-speed PCB
Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias it also often brings great negative effects to the design of the circuit.
In order to reduce the adverse effects caused by the parasitic effects of vias, the following aspects can be done as much as possible in the design:
(1) Considering both cost and signal quality, choose a reasonable size via. For example, for the 6-10 layer memory module PCB design, it is better to use 10/20Mil (drilled/pad) vias. For some high-density small-size boards, you can also try to use 8/18Mil. hole. Under current technical conditions, it is difficult to use smaller vias. For power or ground vias, you can consider using a larger size to reduce impedance.
(2) The two formulas discussed above can be concluded that the use of a thinner PCB is beneficial to reduce the two parasitic parameters of the via. The pins of the power supply and the ground should be punched nearby, and the leads between the vias and the pins should be as short as possible, because they will increase the inductance. At the same time, the power and ground leads should be as thick as possible to reduce impedance.
(3) Try not to change the layers of signal traces on the PCB board, which means to minimize unnecessary vias.
(4) Place some grounded vias near the vias of the signal change layer to provide a close loop for the signal. It is even possible to place a large number of redundant ground vias on the PCB board. Of course, the design needs to be flexible.
The via model discussed earlier is the case where there are pads on each layer. Sometimes, we can reduce or even remove the pads of some layers. Especially when the density of vias is very high, it may lead to the formation of a break groove that separates the loop in the copper layer. To solve this problem, in addition to moving the position of the via, we can also consider placing the via on the copper layer. The pad size is reduced.
How to use vias: Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, improper use of seemingly simple vias often brings great negative effects to the circuit design.